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-- Company: 
-- Engineer: 
-- 
-- Create Date:    19:33:38 02/08/2010 
-- Design Name: 
-- Module Name:    ImageDataIO - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity ImageDataIO is
	Port(	IMG0_I2C_Clk : out std_logic;
			IMG0_I2C_Data : out std_logic;
			IMG0_Data : in std_logic_vector(9 downto 0);
			IMG0_PIXEL_Clk : in std_logic;
			IMG0_ROW_EN : in std_logic;
			IMG0_VSYNC : in std_logic;
			IMG0_RST : out std_logic;
			
			IMG1_I2C_Clk : out std_logic;
			IMG1_I2C_Data : out std_logic;
			IMG1_Data : in std_logic_vector(9 downto 0);
			IMG1_PIXEL_Clk : in std_logic;
			IMG1_ROW_EN : in std_logic;
			IMG1_VSYNC : in std_logic;
			IMG1_RST : out std_logic;
			
			OEM_I2C_Clk : out std_logic;
			OEM_I2C_Data : out std_logic;
			OEM_Data : out std_logic_vector(9 downto 0);
			OEM_PIXEL_Clk : out std_logic;
			OEM_ROW_EN : out std_logic;
			OEM_VSYNC : out std_logic;
			
			Clk_100MHz : in std_logic;
			
			SW : in std_logic_vector(3 downto 0);
			LED : out std_logic_vector(3 downto 0));
end ImageDataIO;

architecture Behavioral of ImageDataIO is

	component ImageController is
	Port(IMG_Data : in std_logic_vector(9 downto 0);
			IMG_PIXEL_Clk : in std_logic;
			IMG_ROW_EN : in std_logic;
			
			OEM_Data : out std_logic_vector(9 downto 0);
			OEM_PIXEL_Clk : out std_logic;
			OEM_ROW_EN : out std_logic;
			OEM_VSYNC : out std_logic;
			
			Row : out std_logic_vector(8 downto 0);
			Col : out std_logic_vector(9 downto 0);
			hsize : in integer;
			vsize : in integer);
	end component;
	
	component ImageCorrection is
	port( DataIn : in std_logic_vector(9 downto 0);
        Clk : in std_logic;
        Row : in std_logic_vector(8 downto 0);
		  Col : in std_logic_vector(9 downto 0);
        DataOut : out std_logic_vector(9 downto 0));
	end component;
	
	signal rst,pclk0,pclk1,rowen0,rowen1,vsync0,vsync1 : std_logic;
	signal current_row,current_vsync,current_pclk : std_logic;
	signal row0,row1 : std_logic_vector(8 downto 0);
   signal col0,col1 : std_logic_vector(9 downto 0);
	signal data0,data1,current_data,fixed0 : std_logic_vector(9 downto 0);
	signal row0_delay,vsync0_delay : std_logic_vector(3 downto 0):=X"0";
	signal row1_delay,vsync1_delay : std_logic_vector(9 downto 0):=(others=>'0');

begin

	Imager0: ImageController port map(IMG0_Data,IMG0_PIXEL_Clk,IMG0_ROW_EN,data0,pclk0,rowen0,vsync0,row0,col0,752,480);
	Imager1: ImageController port map(IMG1_Data,IMG1_PIXEL_Clk,IMG1_ROW_EN,data1,pclk1,rowen1,vsync1,row1,col1,752,480);
	
	Correct0: ImageCorrection port map(data0,IMG0_PIXEL_Clk,row0,col0,fixed0);
	
	row0_delay <= row0_delay(2 downto 0) & rowen0 when rising_edge(pclk0);
	vsync0_delay<=vsync0_delay(2 downto 0) & rowen0 when rising_edge(pclk0);
	row1_delay <= row1_delay(8 downto 0) & rowen1 when rising_edge(pclk1);
	vsync1_delay<=vsync1_delay(8 downto 0) & rowen1 when rising_edge(pclk1);
	
	OEM_ROW_EN<=current_row;
	OEM_VSYNC<=current_vsync;
	OEM_Data<=current_data;
	OEM_PIXEL_Clk<=current_pclk;
	
	IMG0_I2C_Clk<='Z';
	IMG0_I2C_Data<='Z';
	IMG1_I2C_Clk<='Z';
	IMG1_I2C_Data<='Z';
	OEM_I2C_Clk<='Z';
	OEM_I2C_Data<='Z';
	
	LED<="0000";
	
	IMG0_RST<='1';
	IMG1_RST<='1';
	
	switch: process(SW)
	begin
		if SW(3) = '1' then	--choose default camera
			current_data<=data0;	--this is when sw=0
			current_row<=rowen0;
			current_vsync<=vsync0;
			current_pclk<=pclk0;
		else
			current_data<=IMG1_Data;	--this is sw=1
			current_row<=IMG1_ROW_EN;
			current_vsync<=IMG1_VSYNC;
			current_pclk<=IMG1_PIXEL_Clk;
		end if;
	end process;

end Behavioral;

